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W25Q128BV
7.2.13 Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO 0 , IO 1 , IO 2 , and IO 3 . A Quad enable of Status Register-2 must be
executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE
must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the
W25Q128BV at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of F R (see AC
Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address
as shown in Figure 12. The dummy clocks allow the device's internal circuits additional time for setting up
the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins should
be high-impedance prior to the falling edge of the first data out clock.
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
CLK
Mode 0
Instruction (6Bh)
24-Bit Address
IO 0
23
22
21
3
2
1
0
IO 1
IO 2
IO 3
/CS
* = MSB
High Impedance
High Impedance
High Impedance
*
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
CLK
Dummy Clocks
IO 0 switches from
Input to Output
IO 0
IO 1
IO 2
IO 3
0
High Impedance
High Impedance
High Impedance
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Byte 1
Byte 2
Byte 3
Byte 4
Figure 12. Fast Read Quad Output Instruction Sequence Diagram
Publication Release Date: October 03, 2013
- 29 -
Revision H
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